Index: newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h
--- newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h.orig
+++ newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h
@@ -7,7 +7,7 @@
 
 /* Xtensa processor core configuration information.
 
-   Copyright (c) 1999-2016 Tensilica Inc.
+   Copyright (c) 1999-2021 Tensilica Inc.
 
    Permission is hereby granted, free of charge, to any person obtaining
    a copy of this software and associated documentation files (the
@@ -50,7 +50,7 @@
 #define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
 #define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
 #define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	4	/* max instr bytes (3..8) */
 #define XCHAL_HAVE_DEBUG		1	/* debug option */
 #define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
 #define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
@@ -68,6 +68,7 @@
 #define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
 #define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
 #define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_EXCLUSIVE            0	/* L32EX/S32EX instructions */
 #define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
 #define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
 #define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
@@ -95,48 +96,68 @@
 #define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
 #define XCHAL_HAVE_MAC16		1	/* MAC16 package */
 
-#define XCHAL_HAVE_FUSION		 0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP	 0	        /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES	 0	        /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	 0       /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	 0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	 0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS	 0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND	 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI        0     /* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP      0   /* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_FUSION		0	/* Fusion*/
+#define XCHAL_HAVE_FUSION_FP		0	/* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER	0	/* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES		0	/* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC	0	/* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC	0	/* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS	0	/* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS		0	/* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0	/* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI	0	/* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP	0	/* Fusion Soft Bit Demap option */
 #define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5		0	/* HiFi5 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5_NN_MAC		0	/* HiFi5 Audio Engine NN-MAC option */
+#define XCHAL_HAVE_HIFI5_VFPU		0	/* HiFi5 Audio Engine Single-Precision VFPU option */
+#define XCHAL_HAVE_HIFI5_HP_VFPU	0	/* HiFi5 Audio Engine Half-Precision VFPU option */
 #define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
 #define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
 #define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
 #define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3Z		0	/* HiFi3Z Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3Z_VFPU	0	/* HiFi3Z Audio Engine VFPU option */
 #define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
 #define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
 #define XCHAL_HAVE_HIFI_MINI		0	
 
 
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP                 1      /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV             1  /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP           1        /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT            1 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT           1        /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP                        0     /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV            0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP          0       /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT           0        /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT          0       /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		1	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
 
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY    1                 	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU		0       /* user SP floating-point pkg */
+#define XCHAL_HAVE_FP			1	/* single prec floating point */
+#define XCHAL_HAVE_FP_DIV		1	/* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP		1	/* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT		1	/* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT		1	/* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL	/* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY	1	/* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4		        0	/* PDX4 */
+
+#define XCHAL_HAVE_FUSIONG		0    /* FusionG */
+#define XCHAL_HAVE_FUSIONG3		0    /* FusionG3 */
+#define XCHAL_HAVE_FUSIONG6		0    /* FusionG6 */
+#define XCHAL_HAVE_FUSIONG_SP_VFPU	0    /* sp_vfpu option on FusionG */
+#define XCHAL_HAVE_FUSIONG_DP_VFPU	0    /* dp_vfpu option on FusionG */
+#define XCHAL_FUSIONG_SIMD32		0    /* simd32 for FusionG */
+
+#define XCHAL_HAVE_PDX			0    /* PDX */
+#define XCHAL_PDX_SIMD32		0    /* simd32 for PDX */
+#define XCHAL_HAVE_PDX4			0    /* PDX4 */
+#define XCHAL_HAVE_PDX8			0    /* PDX8 */
+#define XCHAL_HAVE_PDX16		0    /* PDX16 */
+
 #define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
 #define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
 #define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
@@ -144,6 +165,7 @@
 #define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
 #define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
 #define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BBENEP_SP_VFPU	0      /* sp_vfpu option on BBE-EP */
 #define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
 #define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
 #define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
@@ -151,10 +173,19 @@
 #define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
 #define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
 #define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_GRIVPEP		0	/* General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM	0       /* Histogram option on GRIVPEP */
 
+#define XCHAL_HAVE_VISION	        0     /* Vision P5/P6 */
+#define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
+#define XCHAL_VISION_TYPE               0     /* Vision P5, P6, or P3 */
+#define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
+#define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6 */
 
+#define XCHAL_HAVE_VISIONC	        0     /* Vision C */
+
 /*----------------------------------------------------------------------
 				MISC
   ----------------------------------------------------------------------*/
@@ -162,8 +193,8 @@
 #define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
 #define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* size of write buffer */
 #define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
+#define XCHAL_DATA_WIDTH		16	/* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY		1	/* d-side pipeline delay
 						   (1 = 5-stage, 2 = 7-stage) */
 #define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
 #define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
@@ -173,34 +204,34 @@
 #define XCHAL_UNALIGNED_LOAD_HW		1	/* unaligned loads work in hw */
 #define XCHAL_UNALIGNED_STORE_HW	1	/* unaligned stores work in hw*/
 
-#define XCHAL_SW_VERSION		1100003	/* sw version of this header */
+#define XCHAL_SW_VERSION		1200012	/* sw version of this header */
 
-#define XCHAL_CORE_ID			"esp32_v3_49_prod"	/* alphanum core name
+#define XCHAL_CORE_ID			"LX7_ESP32_S3_MP"	/* alphanum core name
 						   (CoreID) set in the Xtensa
 						   Processor Generator */
 
-#define XCHAL_BUILD_UNIQUE_ID		0x0005FE96	/* 22-bit sw build ID */
+#define XCHAL_BUILD_UNIQUE_ID		0x00090F1F	/* 22-bit sw build ID */
 
 /*
  *  These definitions describe the hardware targeted by this software.
  */
-#define XCHAL_HW_CONFIGID0		0xC2BCFFFE	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x1CC5FE96	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX6.0.3"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2600	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		3	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION		260003	/* major*100+minor */
-#define XCHAL_HW_REL_LX6		1
-#define XCHAL_HW_REL_LX6_0		1
-#define XCHAL_HW_REL_LX6_0_3		1
+#define XCHAL_HW_CONFIGID0		0xC2F0FFFE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x23090F1F	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX7.0.12"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2700	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		12	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		270012	/* major*100+minor */
+#define XCHAL_HW_REL_LX7		1
+#define XCHAL_HW_REL_LX7_0		1
+#define XCHAL_HW_REL_LX7_0_12		1
 #define XCHAL_HW_CONFIGID_RELIABLE	1
 /*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2600	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	3	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		260003	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2600	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	3	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		260003	/* latest targeted hw */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2700	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	12	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		270012	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2700	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	12	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		270012	/* latest targeted hw */
 
 
 /*----------------------------------------------------------------------
@@ -208,9 +239,9 @@
   ----------------------------------------------------------------------*/
 
 #define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		16	/* D-cache line size in bytes */
 #define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		4	/* log2(D line size in bytes) */
 
 #define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
 #define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
@@ -243,11 +274,14 @@
 				CACHE
   ----------------------------------------------------------------------*/
 
-#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+#define XCHAL_HAVE_PIF			1	/* any outbound bus present */
+
 #define XCHAL_HAVE_AXI			0	/* AXI bus */
+#define XCHAL_HAVE_AXI_ECC		0	/* ECC on AXI bus */
+#define XCHAL_HAVE_ACELITE		0	/* ACELite bus */
 
 #define XCHAL_HAVE_PIF_WR_RESP			0	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			0	/* pif attribute */
+#define XCHAL_HAVE_PIF_REQ_ATTR			1	/* pif attribute */
 
 /*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
 
@@ -264,6 +298,8 @@
 #define XCHAL_DCACHE_LINE_LOCKABLE	0
 #define XCHAL_ICACHE_ECC_PARITY		0
 #define XCHAL_DCACHE_ECC_PARITY		0
+#define XCHAL_ICACHE_ECC_WIDTH		1
+#define XCHAL_DCACHE_ECC_WIDTH		1
 
 /*  Cache access size in bytes (affects operation of SICW instruction):  */
 #define XCHAL_ICACHE_ACCESS_SIZE	1
@@ -278,59 +314,33 @@
 /*----------------------------------------------------------------------
 			INTERNAL I/D RAM/ROMs and XLMI
   ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
+#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		1	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		1	/* number of core data RAMs */
 #define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
+#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
 
-/*  Instruction ROM 0:  */
-#define XCHAL_INSTROM0_VADDR		0x40800000	/* virtual address */
-#define XCHAL_INSTROM0_PADDR		0x40800000	/* physical address */
-#define XCHAL_INSTROM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
 /*  Instruction RAM 0:  */
 #define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
 #define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTRAM0_SIZE		67108864	/* size in bytes */
 #define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM0		1
+#define XCHAL_INSTRAM0_HAVE_IDMA	0	/* idma supported by this local memory */
 
-/*  Instruction RAM 1:  */
-#define XCHAL_INSTRAM1_VADDR		0x40400000	/* virtual address */
-#define XCHAL_INSTRAM1_PADDR		0x40400000	/* physical address */
-#define XCHAL_INSTRAM1_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Data ROM 0:  */
-#define XCHAL_DATAROM0_VADDR		0x3F400000	/* virtual address */
-#define XCHAL_DATAROM0_PADDR		0x3F400000	/* physical address */
-#define XCHAL_DATAROM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_DATAROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATAROM0_BANKS		1	/* number of banks */
-
 /*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x3FF80000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x3FF80000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		524288	/* size in bytes */
+#define XCHAL_DATARAM0_VADDR		0x3C000000	/* virtual address */
+#define XCHAL_DATARAM0_PADDR		0x3C000000	/* physical address */
+#define XCHAL_DATARAM0_SIZE		67108864	/* size in bytes */
 #define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
 #define XCHAL_DATARAM0_BANKS		1	/* number of banks */
+#define XCHAL_HAVE_DATARAM0		1
+#define XCHAL_DATARAM0_HAVE_IDMA	0	/* idma supported by this local memory */
 
-/*  Data RAM 1:  */
-#define XCHAL_DATARAM1_VADDR		0x3F800000	/* virtual address */
-#define XCHAL_DATARAM1_PADDR		0x3F800000	/* physical address */
-#define XCHAL_DATARAM1_SIZE		4194304	/* size in bytes */
-#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM1_BANKS		1	/* number of banks */
+#define XCHAL_HAVE_IDMA			0
+#define XCHAL_HAVE_IDMA_TRANSPOSE	0
 
-/*  XLMI Port 0:  */
-#define XCHAL_XLMI0_VADDR		0x3FF00000	/* virtual address */
-#define XCHAL_XLMI0_PADDR		0x3FF00000	/* physical address */
-#define XCHAL_XLMI0_SIZE		524288	/* size in bytes */
-#define XCHAL_XLMI0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
 #define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
 
 
@@ -450,6 +460,9 @@
 #define XCHAL_INTTYPE_MASK_NMI		0x00004000
 #define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
 #define XCHAL_INTTYPE_MASK_PROFILING	0x00000800
+#define XCHAL_INTTYPE_MASK_IDMA_DONE	0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_ERR	0x00000000
+#define XCHAL_INTTYPE_MASK_GS_ERR	0x00000000
 
 /*  Interrupt numbers assigned to specific interrupt sources:  */
 #define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
@@ -457,7 +470,7 @@
 #define XCHAL_TIMER2_INTERRUPT		16	/* CCOMPARE2 */
 #define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
 #define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
-#define XCHAL_PROFILING_INTERRUPT	11	/* profiling interrupt */
+#define XCHAL_PROFILING_INTERRUPT	11
 
 /*  Interrupt numbers for levels at which only one interrupt is configured:  */
 #define XCHAL_INTLEVEL7_NUM		14
@@ -605,7 +618,7 @@
 
 /*  Misc  */
 #define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
+#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */
 #define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
 
 /*  On-Chip Debug (OCD)  */
@@ -619,7 +632,7 @@
 #define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
 #define XCHAL_TRAX_MEM_SIZE		16384	/* TRAX memory size in bytes */
 #define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */
 #define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
 
 /*  Perf counters  */
@@ -642,11 +655,25 @@
 #define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
 						   [autorefill] and protection)
 						   usable for an MMU-based OS */
-/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
 
+/*  If none of the above last 5 are set, it's a custom TLB configuration.  */
+
 #define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
 #define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
 #define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
+
+/*----------------------------------------------------------------------
+				MPU
+  ----------------------------------------------------------------------*/
+#define XCHAL_HAVE_MPU			0 
+#define XCHAL_MPU_ENTRIES		0
+
+#define XCHAL_MPU_ALIGN_REQ		1	/* MPU requires alignment of entries to background map */
+#define XCHAL_MPU_BACKGROUND_ENTRIES	0	/* number of entries in bg map*/
+#define XCHAL_MPU_BG_CACHEADRDIS	0	/* default CACHEADRDIS for bg */
+ 
+#define XCHAL_MPU_ALIGN_BITS		0
+#define XCHAL_MPU_ALIGN			0
 
 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 
