/* $NetBSD: if_bnxreg.h,v 1.30 2024/02/09 22:08:35 andvar Exp $ */ /* $OpenBSD: if_bnxreg.h,v 1.33 2009/09/05 16:02:28 claudio Exp $ */ /*- * Copyright (c) 2006 Broadcom Corporation * David Christensen . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of Broadcom Corporation nor the name of its contributors * may be used to endorse or promote products derived from this software * without specific prior written consent. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ */ /* General controller flags -- bnx_flags element in bnx_softc */ #define BNX_PCIX_FLAG 0x01 #define BNX_PCI_32BIT_FLAG 0x02 #define BNX_ONE_TDMA_FLAG 0x04 /* Deprecated */ #define BNX_NO_WOL_FLAG 0x08 #define BNX_USING_DAC_FLAG 0x10 #define BNX_USING_MSI_FLAG 0x20 #define BNX_MFW_ENABLE_FLAG 0x40 #define BNX_ACTIVE_FLAG 0x80 #define BNX_ALLOC_PKTS_FLAG 0x100 #define BNX_PCIE_FLAG 0x200 /* PHY specific flags -- bnx_phy_flags element in bnx_softc */ #define BNX_PHY_SERDES_FLAG 0x001 #define BNX_PHY_CRC_FIX_FLAG 0x002 #define BNX_PHY_PARALLEL_DETECT_FLAG 0x004 #define BNX_PHY_2_5G_CAPABLE_FLAG 0x008 #define BNX_PHY_INT_MODE_MASK_FLAG 0x300 #define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 #define BNX_PHY_INT_MODE_LINK_READY_FLAG 0x200 #define BNX_PHY_IEEE_CLAUSE_45_FLAG 0x400 /****************************************************************************/ /* Debugging macros and definitions. */ /****************************************************************************/ #define BNX_CP_LOAD 0x00000001 #define BNX_CP_SEND 0x00000002 #define BNX_CP_RECV 0x00000004 #define BNX_CP_INTR 0x00000008 #define BNX_CP_UNLOAD 0x00000010 #define BNX_CP_RESET 0x00000020 #define BNX_CP_PHY 0x00000040 #define BNX_CP_ALL 0x00FFFFFF #define BNX_CP_MASK 0x00FFFFFF #define BNX_LEVEL_FATAL 0x00000000 #define BNX_LEVEL_WARN 0x01000000 #define BNX_LEVEL_INFO 0x02000000 #define BNX_LEVEL_VERBOSE 0x03000000 #define BNX_LEVEL_EXCESSIVE 0x04000000 #define BNX_LEVEL_MASK 0xFF000000 #define BNX_WARN_LOAD (BNX_CP_LOAD | BNX_LEVEL_WARN) #define BNX_INFO_LOAD (BNX_CP_LOAD | BNX_LEVEL_INFO) #define BNX_VERBOSE_LOAD (BNX_CP_LOAD | BNX_LEVEL_VERBOSE) #define BNX_EXCESSIVE_LOAD (BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE) #define BNX_WARN_SEND (BNX_CP_SEND | BNX_LEVEL_WARN) #define BNX_INFO_SEND (BNX_CP_SEND | BNX_LEVEL_INFO) #define BNX_VERBOSE_SEND (BNX_CP_SEND | BNX_LEVEL_VERBOSE) #define BNX_EXCESSIVE_SEND (BNX_CP_SEND | BNX_LEVEL_EXCESSIVE) #define BNX_WARN_RECV (BNX_CP_RECV | BNX_LEVEL_WARN) #define BNX_INFO_RECV (BNX_CP_RECV | BNX_LEVEL_INFO) #define BNX_VERBOSE_RECV (BNX_CP_RECV | BNX_LEVEL_VERBOSE) #define BNX_EXCESSIVE_RECV (BNX_CP_RECV | BNX_LEVEL_EXCESSIVE) #define BNX_WARN_INTR (BNX_CP_INTR | BNX_LEVEL_WARN) #define BNX_INFO_INTR (BNX_CP_INTR | BNX_LEVEL_INFO) #define BNX_VERBOSE_INTR (BNX_CP_INTR | BNX_LEVEL_VERBOSE) #define BNX_EXCESSIVE_INTR (BNX_CP_INTR | BNX_LEVEL_EXCESSIVE) #define BNX_WARN_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_WARN) #define BNX_INFO_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_INFO) #define BNX_VERBOSE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE) #define BNX_EXCESSIVE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE) #define BNX_WARN_RESET (BNX_CP_RESET | BNX_LEVEL_WARN) #define BNX_INFO_RESET (BNX_CP_RESET | BNX_LEVEL_INFO) #define BNX_VERBOSE_RESET (BNX_CP_RESET | BNX_LEVEL_VERBOSE) #define BNX_EXCESSIVE_RESET (BNX_CP_RESET | BNX_LEVEL_EXCESSIVE) #define BNX_WARN_PHY (BNX_CP_PHY | BNX_LEVEL_WARN) #define BNX_INFO_PHY (BNX_CP_PHY | BNX_LEVEL_INFO) #define BNX_VERBOSE_PHY (BNX_CP_PHY | BNX_LEVEL_VERBOSE) #define BNX_EXTREME_PHY (BNX_CP_PHY | BNX_LEVEL_EXTREME) #define BNX_INSANE_PHY (BNX_CP_PHY | BNX_LEVEL_INSANE) #define BNX_FATAL (BNX_CP_ALL | BNX_LEVEL_FATAL) #define BNX_WARN (BNX_CP_ALL | BNX_LEVEL_WARN) #define BNX_INFO (BNX_CP_ALL | BNX_LEVEL_INFO) #define BNX_VERBOSE (BNX_CP_ALL | BNX_LEVEL_VERBOSE) #define BNX_EXCESSIVE (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE) #define BNX_CODE_PATH(cp) (((cp) & BNX_CP_MASK) & bnx_debug) #define BNX_MSG_LEVEL(lv) \ (((lv) & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK)) #define BNX_LOG_MSG(m) (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m)) #ifdef BNX_DEBUG /* Print a message based on the logging level and code path. */ #define DBPRINT(sc, level, format, args...) \ if (BNX_LOG_MSG(level)) { \ device_printf((sc)->bnx_dev, format, ## args); \ } /* Runs a particular command based on the logging level and code path. */ #define DBRUN(m, args...) \ if (BNX_LOG_MSG(m)) { \ args; \ } /* Runs a particular command based on the logging level. */ #define DBRUNLV(level, args...) \ if (BNX_MSG_LEVEL(level)) { \ args; \ } /* Runs a particular command based on the code path. */ #define DBRUNCP(cp, args...) \ if (BNX_CODE_PATH(cp)) { \ args; \ } /* Runs a particular command based on a condition. */ #define DBRUNIF(cond, args...) \ if (cond) { \ args; \ } #if 0 /* Needed for random() function which is only used in debugging. */ #include #endif /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ #define DB_RANDOMFALSE(defects) (random() > (defects)) #define DB_OR_RANDOMFALSE(defects) || (random() > (defects)) #define DB_AND_RANDOMFALSE(defects) && (random() > (defects)) /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ #define DB_RANDOMTRUE(defects) (random() < (defects)) #define DB_OR_RANDOMTRUE(defects) || (random() < (defects)) #define DB_AND_RANDOMTRUE(defects) && (random() < (defects)) #else #define DBPRINT(level, format, ...) __nothing #define DBRUN(m, ...) __nothing #define DBRUNLV(level, ...) __nothing #define DBRUNCP(cp, ...) __nothing #define DBRUNIF(cond, ...) __nothing #define DB_RANDOMFALSE(defects) __nothing #define DB_OR_RANDOMFALSE(percent) __nothing #define DB_AND_RANDOMFALSE(percent) __nothing #define DB_RANDOMTRUE(defects) __nothing #define DB_OR_RANDOMTRUE(percent) __nothing #define DB_AND_RANDOMTRUE(percent) __nothing #endif /* BNX_DEBUG */ /****************************************************************************/ /* Device identification definitions. */ /****************************************************************************/ #define BRCM_VENDORID 0x14E4 #define BRCM_DEVICEID_BCM5706 0x164A #define BRCM_DEVICEID_BCM5706S 0x16AA #define BRCM_DEVICEID_BCM5708 0x164C #define BRCM_DEVICEID_BCM5708S 0x16AC #define HP_VENDORID 0x103C #define PCI_ANY_ID (uint16_t) (~0U) /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ #define _BNX_CHIP_NUM(chipid) ((chipid) & 0xffff0000) #define BNX_CHIP_NUM(sc) _BNX_CHIP_NUM((sc)->bnx_chipid) #define BNX_CHIP_NUM_5706 0x57060000 #define BNX_CHIP_NUM_5708 0x57080000 #define BNX_CHIP_NUM_5709 0x57090000 #define BNX_CHIP_NUM_5716 0x57160000 #define _BNX_CHIP_REV(chipid) ((chipid) & 0x0000f000) #define BNX_CHIP_REV(sc) _BNX_CHIP_REV((sc)->bnx_chipid) #define BNX_CHIP_REV_Ax 0x00000000 #define BNX_CHIP_REV_Bx 0x00001000 #define BNX_CHIP_REV_Cx 0x00002000 #define BNX_CHIP_METAL(sc) (((sc)->bnx_chipid) & 0x00000ff0) #define BNX_CHIP_BOND(bp) (((sc)->bnx_chipid) & 0x0000000f) #define _BNX_CHIP_ID(chipid) ((chipid) & 0xfffffff0) #define BNX_CHIP_ID(sc) _BNX_CHIP_ID((sc)->bnx_chipid) #define BNX_CHIP_ID_5706_A0 0x57060000 #define BNX_CHIP_ID_5706_A1 0x57060010 #define BNX_CHIP_ID_5706_A2 0x57060020 #define BNX_CHIP_ID_5706_A3 0x57060030 #define BNX_CHIP_ID_5708_A0 0x57080000 #define BNX_CHIP_ID_5708_B0 0x57081000 #define BNX_CHIP_ID_5708_B1 0x57081010 #define BNX_CHIP_ID_5708_B2 0x57081020 #define BNX_CHIP_ID_5709_A0 0x57090000 #define BNX_CHIP_ID_5709_A1 0x57090010 #define BNX_CHIP_ID_5709_B0 0x57091000 #define BNX_CHIP_ID_5709_B1 0x57091010 #define BNX_CHIP_ID_5709_B2 0x57091020 #define BNX_CHIP_ID_5709_C0 0x57092000 #define BNX_CHIP_ID_5716_C0 0x57162000 #define BNX_CHIP_BOND_ID(sc) (((sc)->bnx_chipid) & 0xf) /* A serdes chip will have the first bit of the bond id set. */ #define BNX_CHIP_BOND_ID_SERDES_BIT 0x01 /* shorthand one */ #define BNXNUM(sc) (BNX_CHIP_NUM(sc) >> 16) #define BNXREV(sc) (BNX_CHIP_REV(sc) >> 12) #define BNXMETAL(sc) (BNX_CHIP_METAL(sc) >> 4) struct bnx_type { uint16_t bnx_vid; uint16_t bnx_did; uint16_t bnx_svid; uint16_t bnx_sdid; const char *bnx_name; }; /****************************************************************************/ /* NVRAM Access */ /****************************************************************************/ /* Buffered flash (Atmel: AT45DB011B) specific information */ #define SEEPROM_PAGE_BITS 2 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) #define SEEPROM_PAGE_SIZE 4 #define SEEPROM_TOTAL_SIZE 65536 #define BUFFERED_FLASH_PAGE_BITS 9 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) #define BUFFERED_FLASH_PAGE_SIZE 264 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000 #define SAIFUN_FLASH_PAGE_BITS 8 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) #define SAIFUN_FLASH_PAGE_SIZE 256 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 #define ST_MICRO_FLASH_PAGE_BITS 8 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) #define ST_MICRO_FLASH_PAGE_SIZE 256 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 #define BCM5709_FLASH_PAGE_BITS 8 #define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS) #define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1) #define BCM5709_FLASH_PAGE_SIZE 256 #define NVRAM_TIMEOUT_COUNT 30000 #define BNX_FLASHDESC_MAX 64 #define FLASH_STRAP_MASK (BNX_NVM_CFG1_FLASH_MODE | \ BNX_NVM_CFG1_BUFFER_MODE | BNX_NVM_CFG1_PROTECT_MODE | \ BNX_NVM_CFG1_FLASH_SIZE) #define FLASH_BACKUP_STRAP_MASK (0xf << 26) struct flash_spec { uint32_t strapping; uint32_t config1; uint32_t config2; uint32_t config3; uint32_t write1; #define BNX_NV_BUFFERED 0x00000001 #define BNX_NV_TRANSLATE 0x00000002 #define BNX_NV_WREN 0x00000004 uint32_t flags; uint32_t page_bits; uint32_t page_size; uint32_t addr_mask; uint32_t total_size; const uint8_t *name; }; /****************************************************************************/ /* Shared Memory layout */ /* The BNX bootcode will initialize this data area with port configuration */ /* information which can be accessed by the driver. */ /****************************************************************************/ /* * This value (in milliseconds) determines the frequency of the driver * issuing the PULSE message code. The firmware monitors this periodic * pulse to determine when to switch to an OS-absent mode. */ #define DRV_PULSE_PERIOD_MS 250 /* * This value (in milliseconds) determines how long the driver should * wait for an acknowledgement from the firmware before timing out. Once * the firmware has timed out, the driver will assume there is no firmware * running and there won't be any firmware-driver synchronization during a * driver reset. */ #define FW_ACK_TIME_OUT_MS 1000 #define BNX_DRV_RESET_SIGNATURE 0x00000000 #define BNX_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ #define BNX_DRV_MB 0x00000004 #define BNX_DRV_MSG_CODE 0xff000000 #define BNX_DRV_MSG_CODE_RESET 0x01000000 #define BNX_DRV_MSG_CODE_UNLOAD 0x02000000 #define BNX_DRV_MSG_CODE_SHUTDOWN 0x03000000 #define BNX_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 #define BNX_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 #define BNX_DRV_MSG_CODE_PULSE 0x06000000 #define BNX_DRV_MSG_CODE_DIAG 0x07000000 #define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 #define BNX_DRV_MSG_DATA 0x00ff0000 #define BNX_DRV_MSG_DATA_WAIT0 0x00010000 #define BNX_DRV_MSG_DATA_WAIT1 0x00020000 #define BNX_DRV_MSG_DATA_WAIT2 0x00030000 #define BNX_DRV_MSG_DATA_WAIT3 0x00040000 #define BNX_DRV_MSG_SEQ 0x0000ffff #define BNX_FW_MB 0x00000008 #define BNX_FW_MSG_ACK 0x0000ffff #define BNX_FW_MSG_STATUS_MASK 0x00ff0000 #define BNX_FW_MSG_STATUS_OK 0x00000000 #define BNX_FW_MSG_STATUS_FAILURE 0x00ff0000 #define BNX_LINK_STATUS 0x0000000c #define BNX_LINK_STATUS_INIT_VALUE 0xffffffff #define BNX_LINK_STATUS_LINK_UP 0x1 #define BNX_LINK_STATUS_LINK_DOWN 0x0 #define BNX_LINK_STATUS_SPEED_MASK 0x1e #define BNX_LINK_STATUS_AN_INCOMPLETE (0<<1) #define BNX_LINK_STATUS_10HALF (1<<1) #define BNX_LINK_STATUS_10FULL (2<<1) #define BNX_LINK_STATUS_100HALF (3<<1) #define BNX_LINK_STATUS_100BASE_T4 (4<<1) #define BNX_LINK_STATUS_100FULL (5<<1) #define BNX_LINK_STATUS_1000HALF (6<<1) #define BNX_LINK_STATUS_1000FULL (7<<1) #define BNX_LINK_STATUS_2500HALF (8<<1) #define BNX_LINK_STATUS_2500FULL (9<<1) #define BNX_LINK_STATUS_AN_ENABLED (1<<5) #define BNX_LINK_STATUS_AN_COMPLETE (1<<6) #define BNX_LINK_STATUS_PARALLEL_DET (1<<7) #define BNX_LINK_STATUS_RESERVED (1<<8) #define BNX_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) #define BNX_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) #define BNX_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) #define BNX_LINK_STATUS_PARTNER_AD_100FULL (1<<12) #define BNX_LINK_STATUS_PARTNER_AD_100HALF (1<<13) #define BNX_LINK_STATUS_PARTNER_AD_10FULL (1<<14) #define BNX_LINK_STATUS_PARTNER_AD_10HALF (1<<15) #define BNX_LINK_STATUS_TX_FC_ENABLED (1<<16) #define BNX_LINK_STATUS_RX_FC_ENABLED (1<<17) #define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) #define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) #define BNX_LINK_STATUS_SERDES_LINK (1<<20) #define BNX_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) #define BNX_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) #define BNX_DRV_PULSE_MB 0x00000010 #define BNX_DRV_PULSE_SEQ_MASK 0x00007fff #define BNX_MB_ARGS_0 0x00000014 #define BNX_MB_ARGS_1 0x00000018 /* Indicate to the firmware not to go into the * OS absent when it is not getting driver pulse. * This is used for debugging. */ #define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 #define BNX_DEV_INFO_SIGNATURE 0x00000020 #define BNX_DEV_INFO_SIGNATURE_MAGIC 0x44564900 #define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 #define BNX_DEV_INFO_FEATURE_CFG_VALID 0x01 #define BNX_DEV_INFO_SECONDARY_PORT 0x80 #define BNX_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 #define BNX_SHARED_HW_CFG_PART_NUM 0x00000024 #define BNX_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 #define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 #define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 #define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 #define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff #define BNX_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 #define BNX_SHARED_HW_CFG_CONFIG 0x0000003c #define BNX_SHARED_HW_CFG_DESIGN_NIC 0 #define BNX_SHARED_HW_CFG_DESIGN_LOM 0x1 #define BNX_SHARED_HW_CFG_PHY_COPPER 0 #define BNX_SHARED_HW_CFG_PHY_FIBER 0x2 #define BNX_SHARED_HW_CFG_PHY_2_5G 0x20 #define BNX_SHARED_HW_CFG_PHY_BACKPLANE 0x40 #define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 #define BNX_SHARED_HW_CFG_LED_MODE_MASK 0x300 #define BNX_SHARED_HW_CFG_LED_MODE_MAC 0 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 #define BNX_SHARED_HW_CFG_CONFIG2 0x00000040 #define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 #define BNX_DEV_INFO_BC_REV 0x0000004c #define BNX_PORT_HW_CFG_MAC_UPPER 0x00000050 #define BNX_PORT_HW_CFG_UPPERMAC_MASK 0xffff #define BNX_PORT_HW_CFG_MAC_LOWER 0x00000054 #define BNX_PORT_HW_CFG_CONFIG 0x00000058 #define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 #define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 #define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c #define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 #define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 #define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 #define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c #define BNX_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 #define BNX_DEV_INFO_FORMAT_REV 0x000000c4 #define BNX_DEV_INFO_FORMAT_REV_MASK 0xff000000 #define BNX_DEV_INFO_FORMAT_REV_ID ('A' << 24) #define BNX_SHARED_FEATURE 0x000000c8 #define BNX_SHARED_FEATURE_MASK 0xffffffff #define BNX_PORT_FEATURE 0x000000d8 #define BNX_PORT2_FEATURE 0x00000014c #define BNX_PORT_FEATURE_WOL_ENABLED 0x01000000 #define BNX_PORT_FEATURE_MBA_ENABLED 0x02000000 #define BNX_PORT_FEATURE_ASF_ENABLED 0x04000000 #define BNX_PORT_FEATURE_IMD_ENABLED 0x08000000 #define BNX_PORT_FEATURE_BAR1_SIZE_MASK 0xf #define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 #define BNX_PORT_FEATURE_BAR1_SIZE_64K 0x1 #define BNX_PORT_FEATURE_BAR1_SIZE_128K 0x2 #define BNX_PORT_FEATURE_BAR1_SIZE_256K 0x3 #define BNX_PORT_FEATURE_BAR1_SIZE_512K 0x4 #define BNX_PORT_FEATURE_BAR1_SIZE_1M 0x5 #define BNX_PORT_FEATURE_BAR1_SIZE_2M 0x6 #define BNX_PORT_FEATURE_BAR1_SIZE_4M 0x7 #define BNX_PORT_FEATURE_BAR1_SIZE_8M 0x8 #define BNX_PORT_FEATURE_BAR1_SIZE_16M 0x9 #define BNX_PORT_FEATURE_BAR1_SIZE_32M 0xa #define BNX_PORT_FEATURE_BAR1_SIZE_64M 0xb #define BNX_PORT_FEATURE_BAR1_SIZE_128M 0xc #define BNX_PORT_FEATURE_BAR1_SIZE_256M 0xd #define BNX_PORT_FEATURE_BAR1_SIZE_512M 0xe #define BNX_PORT_FEATURE_BAR1_SIZE_1G 0xf #define BNX_PORT_FEATURE_WOL 0xdc #define BNX_PORT2_FEATURE_WOL 0x150 #define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 #define BNX_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 #define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 #define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf #define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 #define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 #define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 #define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 #define BNX_PORT_FEATURE_MBA 0xe0 #define BNX_PORT2_FEATURE_MBA 0x154 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c #define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 #define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 #define BNX_PORT_FEATURE_IMD 0xe4 #define BNX_PORT2_FEATURE_IMD 0x158 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 #define BNX_PORT_FEATURE_VLAN 0xe8 #define BNX_PORT2_FEATURE_VLAN 0x15c #define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff #define BNX_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 #define BNX_MFW_VER_PTR 0x00000014c #define BNX_BC_STATE_RESET_TYPE 0x000001c0 #define BNX_BC_STATE_RESET_TYPE_SIG 0x00005254 #define BNX_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff #define BNX_BC_STATE_RESET_TYPE_NONE \ (BNX_BC_STATE_RESET_TYPE_SIG | 0x00010000) #define BNX_BC_STATE_RESET_TYPE_PCI \ (BNX_BC_STATE_RESET_TYPE_SIG | 0x00020000) #define BNX_BC_STATE_RESET_TYPE_VAUX \ (BNX_BC_STATE_RESET_TYPE_SIG | 0x00030000) #define BNX_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE #define BNX_BC_STATE_RESET_TYPE_DRV_RESET \ (BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_RESET) #define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD \ (BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_UNLOAD) #define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN \ (BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_SHUTDOWN) #define BNX_BC_STATE_RESET_TYPE_DRV_WOL \ (BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_WOL) #define BNX_BC_STATE_RESET_TYPE_DRV_DIAG \ (BNX_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_DIAG) #define BNX_BC_STATE_RESET_TYPE_VALUE(msg) \ (BNX_BC_STATE_RESET_TYPE_SIG | (msg)) #define BNX_BC_STATE 0x000001c4 #define BNX_BC_STATE_ERR_MASK 0x0000ff00 #define BNX_BC_STATE_SIGN 0x42530000 #define BNX_BC_STATE_SIGN_MASK 0xffff0000 #define BNX_BC_STATE_BC1_START (BNX_BC_STATE_SIGN | 0x1) #define BNX_BC_STATE_GET_NVM_CFG1 (BNX_BC_STATE_SIGN | 0x2) #define BNX_BC_STATE_PROG_BAR (BNX_BC_STATE_SIGN | 0x3) #define BNX_BC_STATE_INIT_VID (BNX_BC_STATE_SIGN | 0x4) #define BNX_BC_STATE_GET_NVM_CFG2 (BNX_BC_STATE_SIGN | 0x5) #define BNX_BC_STATE_APPLY_WKARND (BNX_BC_STATE_SIGN | 0x6) #define BNX_BC_STATE_LOAD_BC2 (BNX_BC_STATE_SIGN | 0x7) #define BNX_BC_STATE_GOING_BC2 (BNX_BC_STATE_SIGN | 0x8) #define BNX_BC_STATE_GOING_DIAG (BNX_BC_STATE_SIGN | 0x9) #define BNX_BC_STATE_RT_FINAL_INIT (BNX_BC_STATE_SIGN | 0x81) #define BNX_BC_STATE_RT_WKARND (BNX_BC_STATE_SIGN | 0x82) #define BNX_BC_STATE_RT_DRV_PULSE (BNX_BC_STATE_SIGN | 0x83) #define BNX_BC_STATE_RT_FIOEVTS (BNX_BC_STATE_SIGN | 0x84) #define BNX_BC_STATE_RT_DRV_CMD (BNX_BC_STATE_SIGN | 0x85) #define BNX_BC_STATE_RT_LOW_POWER (BNX_BC_STATE_SIGN | 0x86) #define BNX_BC_STATE_RT_SET_WOL (BNX_BC_STATE_SIGN | 0x87) #define BNX_BC_STATE_RT_OTHER_FW (BNX_BC_STATE_SIGN | 0x88) #define BNX_BC_STATE_RT_GOING_D3 (BNX_BC_STATE_SIGN | 0x89) #define BNX_BC_STATE_ERR_BAD_VERSION (BNX_BC_STATE_SIGN | 0x0100) #define BNX_BC_STATE_ERR_BAD_BC2_CRC (BNX_BC_STATE_SIGN | 0x0200) #define BNX_BC_STATE_ERR_BC1_LOOP (BNX_BC_STATE_SIGN | 0x0300) #define BNX_BC_STATE_ERR_UNKNOWN_CMD (BNX_BC_STATE_SIGN | 0x0400) #define BNX_BC_STATE_ERR_DRV_DEAD (BNX_BC_STATE_SIGN | 0x0500) #define BNX_BC_STATE_ERR_NO_RXP (BNX_BC_STATE_SIGN | 0x0600) #define BNX_BC_STATE_ERR_TOO_MANY_RBUF (BNX_BC_STATE_SIGN | 0x0700) #define BNX_BC_STATE_CONDITION 0x000001c8 #define BNX_CONDITION_INIT_POR 0x00000001 #define BNX_CONDITION_INIT_VAUX_AVAIL 0x00000002 #define BNX_CONDITION_INIT_PCI_AVAIL 0x00000004 #define BNX_CONDITION_INIT_PCI_RESET 0x00000008 #define BNX_CONDITION_INIT_HD_RESET 0x00000010 /* 5709/16 only */ #define BNX_CONDITION_DRV_PRESENT 0x00000100 #define BNX_CONDITION_LOW_POWER_LINK 0x00000200 #define BNX_CONDITION_CORE_RST_OCCURRED 0x00000400 /* 5709/16 only */ #define BNX_CONDITION_UNUSED 0x00000800 #define BNX_CONDITION_BUSY_EXPROM 0x00001000 /* 5706/08 only */ #define BNX_CONDITION_MFW_RUN_UNKNOWN 0x00000000 #define BNX_CONDITION_MFW_RUN_IPMI 0x00002000 #define BNX_CONDITION_MFW_RUN_UMP 0x00004000 #define BNX_CONDITION_MFW_RUN_NCSI 0x00006000 #define BNX_CONDITION_MFW_RUN_NONE 0x0000e000 #define BNX_CONDITION_MFW_RUN_MASK 0x0000e000 /* 5709/16 only */ #define BNX_CONDITION_PM_STATE_MASK 0x00030000 #define BNX_CONDITION_PM_STATE_FULL 0x00030000 #define BNX_CONDITION_PM_STATE_PREP 0x00020000 #define BNX_CONDITION_PM_STATE_UNPREP 0x00010000 #define BNX_CONDITION_PM_RESERVED 0x00000000 /* 5709/16 only */ #define BNX_CONDITION_RXMODE_KEEP_VLAN 0x00040000 #define BNX_CONDITION_DRV_WOL_ENABLED 0x00080000 #define BNX_CONDITION_PORT_DISABLED 0x00100000 #define BNX_CONDITION_DRV_MAYBE_OUT 0x00200000 #define BNX_CONDITION_DPFW_DEAD 0x00400000 #define BNX_BC_STATE_DEBUG_CMD 0x1dc #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff #define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff #define HOST_VIEW_SHMEM_BASE 0x167c00 /****************************************************************************/ /* Convenience definitions. */ /****************************************************************************/ #define BNX_PRINTF(sc, fmt, ...) \ device_printf((sc)->bnx_dev, fmt, __VA_ARGS__) #define BNX_STATS(x) (u_long) stats->stat_ ## x ## _lo /* * The following data structures are generated from RTL code. * Do not modify any values below this line. */ /****************************************************************************/ /* Do not modify any of the following data structures, they are generated */ /* from RTL code. */ /* */ /* Begin machine generated definitions. */ /****************************************************************************/ /* * tx_bd definition */ struct tx_bd { uint32_t tx_bd_haddr_hi; uint32_t tx_bd_haddr_lo; uint32_t tx_bd_mss_nbytes; #if BYTE_ORDER == BIG_ENDIAN uint16_t tx_bd_vlan_tag; uint16_t tx_bd_flags; #else uint16_t tx_bd_flags; uint16_t tx_bd_vlan_tag; #endif #define TX_BD_FLAGS_CONN_FAULT (1<<0) #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) #define TX_BD_FLAGS_IP_CKSUM (1<<2) #define TX_BD_FLAGS_VLAN_TAG (1<<3) #define TX_BD_FLAGS_COAL_NOW (1<<4) #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) #define TX_BD_FLAGS_END (1<<6) #define TX_BD_FLAGS_START (1<<7) #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) #define TX_BD_FLAGS_SW_FLAGS (1<<13) #define TX_BD_FLAGS_SW_SNAP (1<<14) #define TX_BD_FLAGS_SW_LSO (1<<15) }; /* * rx_bd definition */ struct rx_bd { uint32_t rx_bd_haddr_hi; uint32_t rx_bd_haddr_lo; uint32_t rx_bd_len; uint32_t rx_bd_flags; #define RX_BD_FLAGS_NOPUSH (1<<0) #define RX_BD_FLAGS_DUMMY (1<<1) #define RX_BD_FLAGS_END (1<<2) #define RX_BD_FLAGS_START (1<<3) }; /* * status_block definition */ struct status_block { uint32_t status_attn_bits; #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) uint32_t status_attn_bits_ack; #if BYTE_ORDER == BIG_ENDIAN uint16_t status_tx_quick_consumer_index0; uint16_t status_tx_quick_consumer_index1; uint16_t status_tx_quick_consumer_index2; uint16_t status_tx_quick_consumer_index3; uint16_t status_rx_quick_consumer_index0; uint16_t status_rx_quick_consumer_index1; uint16_t status_rx_quick_consumer_index2; uint16_t status_rx_quick_consumer_index3; uint16_t status_rx_quick_consumer_index4; uint16_t status_rx_quick_consumer_index5; uint16_t status_rx_quick_consumer_index6; uint16_t status_rx_quick_consumer_index7; uint16_t status_rx_quick_consumer_index8; uint16_t status_rx_quick_consumer_index9; uint16_t status_rx_quick_consumer_index10; uint16_t status_rx_quick_consumer_index11; uint16_t status_rx_quick_consumer_index12; uint16_t status_rx_quick_consumer_index13; uint16_t status_rx_quick_consumer_index14; uint16_t status_rx_quick_consumer_index15; uint16_t status_completion_producer_index; uint16_t status_cmd_consumer_index; uint16_t status_idx; uint16_t status_unused; #elif BYTE_ORDER == LITTLE_ENDIAN uint16_t status_tx_quick_consumer_index1; uint16_t status_tx_quick_consumer_index0; uint16_t status_tx_quick_consumer_index3; uint16_t status_tx_quick_consumer_index2; uint16_t status_rx_quick_consumer_index1; uint16_t status_rx_quick_consumer_index0; uint16_t status_rx_quick_consumer_index3; uint16_t status_rx_quick_consumer_index2; uint16_t status_rx_quick_consumer_index5; uint16_t status_rx_quick_consumer_index4; uint16_t status_rx_quick_consumer_index7; uint16_t status_rx_quick_consumer_index6; uint16_t status_rx_quick_consumer_index9; uint16_t status_rx_quick_consumer_index8; uint16_t status_rx_quick_consumer_index11; uint16_t status_rx_quick_consumer_index10; uint16_t status_rx_quick_consumer_index13; uint16_t status_rx_quick_consumer_index12; uint16_t status_rx_quick_consumer_index15; uint16_t status_rx_quick_consumer_index14; uint16_t status_cmd_consumer_index; uint16_t status_completion_producer_index; uint16_t status_unused; uint16_t status_idx; #endif }; /* * statistics_block definition */ struct statistics_block { uint32_t stat_IfHCInOctets_hi; uint32_t stat_IfHCInOctets_lo; uint32_t stat_IfHCInBadOctets_hi; uint32_t stat_IfHCInBadOctets_lo; uint32_t stat_IfHCOutOctets_hi; uint32_t stat_IfHCOutOctets_lo; uint32_t stat_IfHCOutBadOctets_hi; uint32_t stat_IfHCOutBadOctets_lo; uint32_t stat_IfHCInUcastPkts_hi; uint32_t stat_IfHCInUcastPkts_lo; uint32_t stat_IfHCInMulticastPkts_hi; uint32_t stat_IfHCInMulticastPkts_lo; uint32_t stat_IfHCInBroadcastPkts_hi; uint32_t stat_IfHCInBroadcastPkts_lo; uint32_t stat_IfHCOutUcastPkts_hi; uint32_t stat_IfHCOutUcastPkts_lo; uint32_t stat_IfHCOutMulticastPkts_hi; uint32_t stat_IfHCOutMulticastPkts_lo; uint32_t stat_IfHCOutBroadcastPkts_hi; uint32_t stat_IfHCOutBroadcastPkts_lo; uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; uint32_t stat_Dot3StatsCarrierSenseErrors; uint32_t stat_Dot3StatsFCSErrors; uint32_t stat_Dot3StatsAlignmentErrors; uint32_t stat_Dot3StatsSingleCollisionFrames; uint32_t stat_Dot3StatsMultipleCollisionFrames; uint32_t stat_Dot3StatsDeferredTransmissions; uint32_t stat_Dot3StatsExcessiveCollisions; uint32_t stat_Dot3StatsLateCollisions; uint32_t stat_EtherStatsCollisions; uint32_t stat_EtherStatsFragments; uint32_t stat_EtherStatsJabbers; uint32_t stat_EtherStatsUndersizePkts; uint32_t stat_EtherStatsOverrsizePkts; uint32_t stat_EtherStatsPktsRx64Octets; uint32_t stat_EtherStatsPktsRx65Octetsto127Octets; uint32_t stat_EtherStatsPktsRx128Octetsto255Octets; uint32_t stat_EtherStatsPktsRx256Octetsto511Octets; uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets; uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; uint32_t stat_EtherStatsPktsTx64Octets; uint32_t stat_EtherStatsPktsTx65Octetsto127Octets; uint32_t stat_EtherStatsPktsTx128Octetsto255Octets; uint32_t stat_EtherStatsPktsTx256Octetsto511Octets; uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets; uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; uint32_t stat_XonPauseFramesReceived; uint32_t stat_XoffPauseFramesReceived; uint32_t stat_OutXonSent; uint32_t stat_OutXoffSent; uint32_t stat_FlowControlDone; uint32_t stat_MacControlFramesReceived; uint32_t stat_XoffStateEntered; uint32_t stat_IfInFramesL2FilterDiscards; uint32_t stat_IfInRuleCheckerDiscards; uint32_t stat_IfInFTQDiscards; uint32_t stat_IfInMBUFDiscards; uint32_t stat_IfInRuleCheckerP4Hit; uint32_t stat_CatchupInRuleCheckerDiscards; uint32_t stat_CatchupInFTQDiscards; uint32_t stat_CatchupInMBUFDiscards; uint32_t stat_CatchupInRuleCheckerP4Hit; uint32_t stat_GenStat00; uint32_t stat_GenStat01; uint32_t stat_GenStat02; uint32_t stat_GenStat03; uint32_t stat_GenStat04; uint32_t stat_GenStat05; uint32_t stat_GenStat06; uint32_t stat_GenStat07; uint32_t stat_GenStat08; uint32_t stat_GenStat09; uint32_t stat_GenStat10; uint32_t stat_GenStat11; uint32_t stat_GenStat12; uint32_t stat_GenStat13; uint32_t stat_GenStat14; uint32_t stat_GenStat15; }; /* * l2_fhdr definition */ struct l2_fhdr { uint32_t l2_fhdr_status; #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) #define L2_FHDR_STATUS_RULE_P2 (1<<3) #define L2_FHDR_STATUS_RULE_P3 (1<<4) #define L2_FHDR_STATUS_RULE_P4 (1<<5) #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) #define L2_FHDR_STATUS_RSS_HASH (1<<8) #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) #define L2_FHDR_ERRORS_BAD_CRC (1<<17) #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) uint32_t l2_fhdr_hash; #if BYTE_ORDER == BIG_ENDIAN uint16_t l2_fhdr_pkt_len; uint16_t l2_fhdr_vlan_tag; uint16_t l2_fhdr_ip_xsum; uint16_t l2_fhdr_tcp_udp_xsum; #elif BYTE_ORDER == LITTLE_ENDIAN uint16_t l2_fhdr_vlan_tag; uint16_t l2_fhdr_pkt_len; uint16_t l2_fhdr_tcp_udp_xsum; uint16_t l2_fhdr_ip_xsum; #endif }; /* * l2_context definition */ #define BNX_L2CTX_TYPE 0x00000000 #define BNX_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) #define BNX_L2CTX_TYPE_TYPE (0xf<<28) #define BNX_L2CTX_TYPE_TYPE_EMPTY (0<<28) #define BNX_L2CTX_TYPE_TYPE_L2 (1<<28) #define BNX_L2CTX_TYPE_XI 0x00000080 #define BNX_L2CTX_TX_HOST_BIDX 0x00000088 #define BNX_L2CTX_EST_NBD 0x00000088 #define BNX_L2CTX_CMD_TYPE 0x00000088 #define BNX_L2CTX_CMD_TYPE_TYPE (0xf<<24) #define BNX_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) #define BNX_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) #define BNX_L2CTX_TX_HOST_BSEQ 0x00000090 #define BNX_L2CTX_TSCH_BSEQ 0x00000094 #define BNX_L2CTX_TBDR_BSEQ 0x00000098 #define BNX_L2CTX_TBDR_BOFF 0x0000009c #define BNX_L2CTX_TBDR_BIDX 0x0000009c #define BNX_L2CTX_TBDR_BHADDR_HI 0x000000a0 #define BNX_L2CTX_TBDR_BHADDR_LO 0x000000a4 #define BNX_L2CTX_TXP_BOFF 0x000000a8 #define BNX_L2CTX_TXP_BIDX 0x000000a8 #define BNX_L2CTX_TXP_BSEQ 0x000000ac #define BNX_L2CTX_CMD_TYPE_XI 0x00000240 #define BNX_L2CTX_TBDR_BHADDR_HI_XI 0x00000258 #define BNX_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c /* * l2_bd_chain_context definition */ #define BNX_L2CTX_BD_PRE_READ 0x00000000 #define BNX_L2CTX_CTX_SIZE 0x00000000 #define BNX_L2CTX_CTX_TYPE 0x00000000 #define BNX_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) #define BNX_L2CTX_HOST_BDIDX 0x00000004 #define BNX_L2CTX_HOST_BSEQ 0x00000008 #define BNX_L2CTX_NX_BSEQ 0x0000000c #define BNX_L2CTX_NX_BDHADDR_HI 0x00000010 #define BNX_L2CTX_NX_BDHADDR_LO 0x00000014 #define BNX_L2CTX_NX_BDIDX 0x00000018 /* * l2_rx_context definition (5706, 5708, 5709, and 5716) */ #define BNX_L2CTX_RX_WATER_MARK 0x00000000 #define BNX_L2CTX_RX_LO_WATER_MARK_SHIFT 0 #define BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT 32 #define BNX_L2CTX_RX_LO_WATER_MARK_SCALE 4 #define BNX_L2CTX_RX_LO_WATER_MARK_DIS 0 #define BNX_L2CTX_RX_HI_WATER_MARK_SHIFT 4 #define BNX_L2CTX_RX_HI_WATER_MARK_SCALE 16 #define BNX_L2CTX_RX_WATER_MARKS_MSK 0x000000ff #define BNX_L2CTX_RX_BD_PRE_READ 0x00000000 #define BNX_L2CTX_RX_BD_PRE_READ_SHIFT 8 #define BNX_L2CTX_RX_CTX_SIZE 0x00000000 #define BNX_L2CTX_RX_CTX_SIZE_SHIFT 16 #define BNX_L2CTX_RX_CTX_TYPE_SIZE_L2 \ ((0x20/20)<> (BCM_PAGE_BITS - 4)) #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) #define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) #define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) /* Context size. */ #define BNX_CTX_SHIFT 7 #define BNX_CTX_SIZE (1 << BNX_CTX_SHIFT) #define BNX_CTX_MASK (BNX_CTX_SIZE - 1) #define GET_CID_ADDR(_cid) ((_cid) << BNX_CTX_SHIFT) #define GET_CID(_cid_addr) ((_cid_addr) >> BNX_CTX_SHIFT) #define BNX_PHY_CTX_SHIFT 6 #define BNX_PHY_CTX_SIZE (1 << BNX_PHY_CTX_SHIFT) #define BNX_PHY_CTX_MASK (BNX_PHY_CTX_SIZE - 1) #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_BNX_CTX_SHIFT) #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_BNX_CTX_SHIFT) #define BNX_MB_KERNEL_CTX_SHIFT 8 #define BNX_MB_KERNEL_CTX_SIZE (1 << BNX_MB_KERNEL_CTX_SHIFT) #define BNX_MB_KERNEL_CTX_MASK (BNX_MB_KERNEL_CTX_SIZE - 1) #define BNX_MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << BNX_MB_KERNEL_CTX_SHIFT)) #define MAX_CID_CNT 0x4000 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) #define INVALID_CID_ADDR 0xffffffff #define TX_CID 16 #define RX_CID 0 #define MB_TX_CID_ADDR BNX_MB_GET_CID_ADDR(TX_CID) #define MB_RX_CID_ADDR BNX_MB_GET_CID_ADDR(RX_CID) /****************************************************************************/ /* BNX Processor Firmware Load Definitions */ /****************************************************************************/ struct cpu_reg { uint32_t mode; uint32_t mode_value_halt; uint32_t mode_value_sstep; uint32_t state; uint32_t state_value_clear; uint32_t gpr0; uint32_t evmask; uint32_t pc; uint32_t inst; uint32_t bp; uint32_t spad_base; uint32_t mips_view_base; }; struct fw_info { uint32_t ver_major; uint32_t ver_minor; uint32_t ver_fix; uint32_t start_addr; /* Text section. */ uint32_t text_addr; uint32_t text_len; uint32_t text_index; const uint32_t *text; /* Data section. */ uint32_t data_addr; uint32_t data_len; uint32_t data_index; const uint32_t *data; /* SBSS section. */ uint32_t sbss_addr; uint32_t sbss_len; uint32_t sbss_index; const uint32_t *sbss; /* BSS section. */ uint32_t bss_addr; uint32_t bss_len; uint32_t bss_index; const uint32_t *bss; /* Read-only section. */ uint32_t rodata_addr; uint32_t rodata_len; uint32_t rodata_index; const uint32_t *rodata; }; struct bnx_rv2p_header { int bnx_rv2p_proc1len; int bnx_rv2p_proc2len; /* * Followed by blocks of data, each sized according to * the (rather obvious) block length stated above. */ }; /* * The RV2P block must be configured for the system * page size, or more specifically, the number of * usable rx_bd's per page, and should be called * as follows prior to loading the RV2P firmware: * * BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE) * * The default value is 0xFF. */ #define BNX_RV2P_PROC2_MAX_BD_PAGE_LOC 5 #define BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(_rv2p, _v) { \ _rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] = \ (_rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (_v); \ } #define RV2P_PROC1 0 #define RV2P_PROC2 1 #define BNX_MIREG(x) (((x) & 0x1F) << 16) #define BNX_MIPHY(x) (((x) & 0x1F) << 21) #define BNX_PHY_TIMEOUT 50 #define BNX_NVRAM_SIZE 0x200 #define BNX_NVRAM_MAGIC 0x669955aa #define BNX_CRC32_RESIDUAL 0xdebb20e3 #define BNX_TX_TIMEOUT 5 #define BNX_MAX_SEGMENTS 8 #define BNX_DMA_ALIGN 8 #define BNX_DMA_BOUNDARY 0 #define BNX_MIN_MTU 60 #define BNX_MIN_ETHER_MTU 64 #define BNX_MAX_STD_MTU 1500 #define BNX_MAX_STD_ETHER_MTU 1518 #define BNX_MAX_STD_ETHER_MTU_VLAN 1522 #define BNX_MAX_JUMBO_MTU 9000 #define BNX_MAX_JUMBO_ETHER_MTU 9018 #define BNX_MAX_JUMBO_ETHER_MTU_VLAN 9022 #define BNX_MAX_MRU MCLBYTES #define BNX_MAX_JUMBO_MRU 9216